Product Summary
The UPD720101GJ is a host controller. It complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller Interface Specification for full-/low-speed signaling and Intel’s Enhanced Host Controller Interface Specification for high-speed signaling and works up to 480 Mbps. The UPD720101GJ is integrated 3 host controller cores with PCI interface and USB2.0 transceivers into a single chip.
Parametrics
UPD720101GJ absolute maximum ratings: (1)Power supply voltage, VDD: -0.5 to +4.6V; (2)Power supply voltage, AVDD -0.5 to +4.6V; (3)Power supply voltage, VDD_PCI -0.5 to +6.0V; (4)Input voltage, 5 V buffer, VI: -0.5 to +6.6V; (5)Input voltage, 3.3 V buffer, VI: -0.5 to +4.6V; (6)Output voltage, 5 V buffer, VO: -0.5 to +6.6V; (7)Output voltage, 3.3 V buffer, VO: -0.5 to +4.6V; (8)Operating ambient temperature, TA: 0 to +70℃; (9)Storage temperature, Tstg: -65 to +150℃.
Features
UPD720101GJ features: (1)Compliant with Universal Serial Bus Specification Revision 2.0 (Data rate 1.5/12/480 Mbps); (2)Compliant with Open Host Controller Interface Specification for USB Rev 1.0a; (3)Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0; (4)Root hub with 5 (max.) downstream facing ports which are shared by OHCI and EHCI host controller cores.; (5)Configurable number of downstream facing ports (2 to 5); (6)32-bit 33 MHz host interface compliant to PCI Specification release 2.2; (7)Supports PCI Mobile Design Guide Revision 1.1; (8)Supports PCI-Bus Power Management Interface Specification release 1.1; (9)PCI bus bus-master access; (10)Operational registers direct-mapped to PCI memory space; (11)3.3V power supply, PCI signal pins have 5 V tolerant circuit.
Diagrams
Image | Part No | Mfg | Description | Pricing (USD) |
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UPD720101GJ-UEN-A |
HOST CTLR USB 2.0 144-LQFP |
Data Sheet |
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